Details

Subject(s)

• Integrated circuits—Very large scale integration—Design and construction—Data processing [Browse]
• Integrated circuits—Wafer-scale integration—Design and construction—Data processing [Browse]
• Integrated circuits—Very large scale integration—Reliability [Browse]
• Integrated circuits—Wafer-scale integration—Reliability [Browse]
• Fault-tolerant computing [Browse]

Related name

• Ciciani, Bruno [Browse]

Summary note

• Low manufacturing yield and dependability (reliability, availability, and performability) are problems of increasing importance as the densities of integrated circuits increase. This book furnishes you with engineering methodologies so that you can evaluate the cost-benefit ratio of fault-tolerant mechanisms used in VLSI/WSI systems. It focuses in particular on manufacturing fault analysis and yield evaluation.
• A practical understanding of these concepts and their application can help to reduce the chance of having device failures.
• This book is divided into five chapters. The first chapter introduces and presents an overview of yield enhancement techniques, manufacturing defect and fault modeling, yield evaluation methodologies, and cost-benefit ratio evaluation methodologies of fault-tolerant mechanisms. Each of the other four chapters contains a collection of papers covering these four research areas.
• These chapters begin with an introduction to the papers, present abstracts, and provide further references for a complete study of the reprinted papers that follow.

Bibliographic references

Includes bibliographical references.

Contents

• An Introduction to Manufacturing Yield of VLSI/WSI Systems
• Fault Tolerance in VLSI Circuits / I. Koren and A. D. Singh
• A Review of Fault-Tolerant Techniques for the Enhancement of Integrated Circuit Yield / W. R. Moore
• Wafer-Scale Integration Using Restructurable VLSI / A. H. Anderson, J. I. Raffel and P. W. Wyatt
• TRAM: A Design Methodology for High-Performance, Easily Testable, Multimegabit RAM's / N. T. Jarwala and D. K. Pradhan
• Optimized Redundancy Selection Based on Failure-Related Yield Model for 64-Mb DRAM and Beyond / S. Kikuda, H. Miyamoto, S. Mori, M. Niiro and M. Yamada
• On the Design of High-Yield Reconfigurable PLA's / D. S. Ha and V. P. Kumar
• A Reconfigurable Modular Fault Tolerant Binary Tree Architecture / A. D. Singh
• Efficient Algorithms for Reconfiguration in VLSI/WSI Arrays / V. P. Roychowdhury, J. Bruck and T. Kailath --
• Configuring a Wafer-Scale Two-Dimensional Array of Single-Bit Processors / A. Boubekeur, J.-L. Patry, G. Saucier and J. Trilhe
• Integrated Circuit Yield Statistics / C. H. Stapper, F. M. Armstrong and K. Saji
• VLSI Yield Prediction and Estimation: A Unified Framework / W. Maly, A. J. Strojwas and S. W. Director
• Computer-Aided Design for VLSI Circuit Manufacturability / W. Maly
• Yield Model for Productivity Optimization of VLSI Memory Chips with Redundancy and Partially Good Product / C. H. Stapper, A. N. McLaren and M. Dreckmann
• The Effect of Scaling on the Yield of VLSI Circuits / I. Koren
• Defect Size Distribution in VLSI Chips / R. Glang
• Large-Area Fault Clusters and Fault Tolerance in VLSI Circuits: A Review / C. H. Stapper
• Small-Area Fault Clusters and Fault Tolerance in VLSI Circuits / C. H. Stapper
• Modeling Defect Spatial Distribution / F. J. Meyer and D. K. Pradhan --
• A Discussion of Yield Modeling with Defect Clustering, Circuit Repair, and Circuit Redundancy / T. L. Michalka, R. C. Varshney and J. D. Meindl
• A Unified Negative-Binomial Distribution for Yield Analysis of Defect-Tolerant Circuits / I. Koren, Z. Koren and C. H. Stapper
• Architectural Yield Optimization for WSI / J. C. Harden and N. R. Strader
• Yield Models for Defect-Tolerant VLSI Circuits: A Review / I. Koren and C. H. Stapper
• A Markov Chain-Based Yield Formula for VLSI Fault-Tolerant Chips / B. Ciciani and G. Iazeolla
• Modeling the Effects of Imperfect Production Testing on Reconfigurable VLSI Chips / B. Ciciani
• Improved Yield Models for Fault-Tolerant Memory Chips / C. H. Stapper
• VLASIC: A Catastrophic Fault Yield Simulator for Integrated Circuits / H. Walker and S. W. Director
• A Design and Yield Evaluation Technique for Wafer-Scale Memory / K. Yamashita and S. Ikehara --
• Fault-Tolerant Design for VLSI: Effect of Interconnect Requirements on Yield Improvement of VLSI Designs / T. E. Mangir and A. Avizienis
• On Area and Yield Considerations for Fault-Tolerant VLSI Processor Arrays / I. Koren and M. A. Breuer
• Gracefully Degradable Processor Arrays / J. A. B. Fortes and C. S. Raghavendra
• Modeling the Effect of Redundancy on Yield and Performance of VLSI Systems / I. Koren and D. K. Pradhan
• A Reconfiguration Scheme for Yield Enhancement of Large Area Binary Tree Architectures / M. C. Howells and V. K. Agarwal
• Fault-Tolerance Considerations for Redundant Binary-Tree-Dynamic Random-Access-Memory (RAM) Chips / B. Ciciani.

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ISBN

• 0818662905 (paper)
• 0818662913 (M/fiche)
• 0818662921 (case)

LCCN

94020185

OCLC

34971155

RCP

C - O

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