LEADER 04019cam a2200577Ii 4500001 99125224230806421 005 20240418104722.0 006 m o d | 007 cr -n--------- 008 180331t20162016fluad ob 001 0 eng d 020 9781351830980 020 1351830988 020 9781315215099 020 1315215098 020 9781482255898 020 1482255898 024 7 10.1201/b18976 |2doi 035 (CKB)3710000000478462 035 (EBL)4003250 035 (SSID)ssj0001622678 035 (PQKBManifestationID)16358955 035 (PQKBTitleCode)TC0001622678 035 (PQKBWorkID)14925971 035 (PQKB)10980772 035 (MiAaPQ)EBC4003250 035 (OCoLC)925551154 035 (FlBoTFG)9781315215099 035 (EXLCZ)993710000000478462 040 FlBoTFG |cFlBoTFG |erda 041 eng 050 4 TK7871.85 |b.E44 2016 082 621.3/81 245 00 Electrostatic discharge protection : |badvances and applications / |cedited by Juin J. Liou, University of Central Florida, Orlando, USA ; Krzysztof Iniewski, managing editor, CMOS Emerging Technologies Research Incorporated, Vancouver, British Columbia. 250 2nd ed. 264 1 Boca Raton, Florida : |bCRC Press, |c[2016] 264 4 |c©2016 300 1 online resource (314 p.) 336 text |btxt 337 computer |bc 338 online resource |bcr 490 1 Devices, Circuits, and Systems 500 Description based upon print version of record. 504 Includes bibliographical references. 505 0 chapter 1. Introduction to electrostatic discharge protection / Juin J. Liou -- chapter 2. Design of component-level on-chip ESD protection for integrated circuits / Charvaka Duvvury -- chapter 3. ESD and EOS : failure mechanisms and reliability / Nathaniel Peachey and Kevin Mello -- chapter 4. ESD, EOS, and latch-up test methods and associated reliability concerns / Alan W. Righter -- chapter 5. Design of power-rail ESD clamp circuits with gate-leakage consideration in nanoscale CMOS technology / Ming-Dou Ker and Chih-Ting Yeh -- chapter 6. ESD protection in automotive integrated circuit applications / Javier A. Salcedo and Jean-Jacques Hajjar -- chapter 7. ESD sensitivity of GaN-based electronic devices / Gaudenzio Meneghesso, Matteo Meneghini, and Enrico Zanoni -- chapter 8. ESD protection circuits using NMOS parasitic bipolar transistor / Teruo Suzuki -- chapter 9. ESD development in foundry processes / Jim Vinson -- chapter 10. Compact modeling of semiconductor devices for electrostatic discharge protection applications / Zhenghao Gan and Waisum wong -- chapter 11. Advanced TCAD methods for system-level ESD design / Vladislav A. Vashchenko and Andrei A. Shibkov -- chapter 12. ESD protection of failsafe and voltage-tolerant signal pins / David L. Catlett, Jr., Roger A. Cline, and Ponnarith Pok -- chapter 13. ESD design and optimization in advanced CMOS SOI technology / You Li. 520 This book delivers timely coverage of component- and system-level electrostatic discharge (ESD) protection for semiconductor devices and integrated circuits. Illustrated with tables, figures, and case studies, the text brings together contributions from internationally respected researchers and engineers with expertise in ESD design, optimization, modeling, simulation, and characterization. It provides readers with a deeper understanding of ESD events, ESD protection design principles, important aspects of the modeling and simulation of ESD protection solutions, and vital processes including Si CMOS, Si BCD, Si SOI, and GaN technologies. 546 English 588 Description based on online resource; title from PDF title page (ebrary, viewed December 12, 2015). 650 0 Semiconductors |xProtection. 650 0 Electric discharges. 650 0 Integrated circuits |xProtection. 700 1 Liou, Juin J., |eeditor. 700 1 Iniewski, Krzysztof, |d1960- |eeditor. 776 08 |z9781138893078 776 08 |z1138893072 776 08 |z9781482255881 776 08 |z148225588X 830 0 Devices, circuits, and systems. 906 BOOK